diff --git a/src/lib.rs b/src/lib.rs
index dff5ba7..2c0d865 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -227,6 +227,14 @@ enum Register {
     Clk5 = 21,
     Clk6 = 22,
     Clk7 = 23,
+    Clk0Phoff = 165,
+    Clk1Phoff,
+    Clk2Phoff,
+    Clk3Phoff,
+    Clk4Phoff,
+    Clk5Phoff,
+    Clk6Phoff, //Not in datasheet
+    Clk7Phoff, //Not in datasheet
     PLLReset = 177,
     CrystalLoad = 183,
 }
@@ -367,6 +375,8 @@ pub trait Si5351 {
     fn setup_multisynth_int(&mut self, ms: Multisynth, mult: u16, r_div: OutputDivider) -> Result<(), Error>;
     fn setup_multisynth(&mut self, ms: Multisynth, div: u16, num: u32, denom: u32, r_div: OutputDivider) -> Result<(), Error>;
     fn select_clock_pll(&mut self, clocl: ClockOutput, pll: PLL);
+
+    fn set_phase_offset(&mut self, clk: ClockOutput, phase_offset: u8) -> Result<(), Error>;
 }
 
 impl<I2C, E> Si5351Device<I2C>
@@ -555,6 +565,22 @@ impl<I2C, E> Si5351 for Si5351Device<I2C> where
         Ok(())
     }
 
+    fn set_phase_offset(&mut self, clk: ClockOutput, phase_offset: u8) -> Result<(), Error> {
+        if phase_offset & 1<<7 > 0 {return Err(Error::InvalidParameter);}
+        let reg = match clk {
+            ClockOutput::Clk0 => Register::Clk0Phoff,
+            ClockOutput::Clk1 => Register::Clk1Phoff,
+            ClockOutput::Clk2 => Register::Clk2Phoff,
+            ClockOutput::Clk3 => Register::Clk3Phoff,
+            ClockOutput::Clk4 => Register::Clk4Phoff,
+            ClockOutput::Clk5 => Register::Clk5Phoff,
+            ClockOutput::Clk6 => Register::Clk6Phoff,
+            ClockOutput::Clk7 => Register::Clk7Phoff,
+        };
+        self.write_register(reg, phase_offset)?;
+        Ok(())
+    }
+
     fn set_clock_enabled(&mut self, clk: ClockOutput, enabled: bool) {
         let bit = 1u8 << clk.ix();
         if enabled {